1. Field of the Invention
The invention relates to a control apparatus applied to a pulse width modulation (PWM) control inverter for converting DC power into AC power, a PWM control converter for converting AC power into DC power, and the like.
2. Description of the Related Art
For general background into the subject matter of the invention, reference is made to co-pending application Ser. No. 07/841,816, filed Feb. 26, 1992 entitled "Control Device of Neutral Point Clamped Power Inverter Apparatus," incorporated herein by reference.
A pulse width modulation control inverter uses self-quenching type switching elements such as gate turn-off (GTO) thyristors.
As shown in FIG. 1, the inverter control apparatus comprises a controller 300, a comparator 301 and a pulse correction circuit 302. The controller 300 outputs a voltage reference signals V*. The comparator 301 compares the voltage reference signals V* and carrier signals V.sub.CP and V.sub.CN, and outputs output signals V.sub.CMP. The pulse correction circuit 302 corrects the output signals V.sub.CMP from the comparator 301, and outputs gate signals V.sub.G. These gate signals are used to control the switching elements, e.g., GTOs in the inverter as is well known in the prior art, e.g., FIG. 13.
As shown in FIG. 2, the pulse correction circuit 302 operates to correct the output signal V.sub.CMP when the width of the output signal V.sub.CMP is equal to or less than a minimum ON pulse width T.sub.O (namely, the absolute value of the voltage reference signal V* is equal to or less than a minimum voltage reference .+-.V.sub.min). As a result, the minimum width of the gate signal V.sub.G is not less than the minimum ON pulse width T.sub.O.
However, the control apparatus cannot control the output voltage at the low voltage regime which thus may also be called an uncontrolled regime. The low voltage regime means a region in which the width of the output signals V.sub.CMP is equal to or less than the minimum ON pulse width T.sub.O. To avoid using a pulse less than the minimum ON time, the prior art teaches modification of the comparator signals V.sub.CMP so as to produce the constant pulse width gate signals V.sub.G in the uncontrolled regime. However, using a fixed width gate pulse means that the width of the phase voltage of the inverter may not be variably controlled as would be desirable so as to control the inverter throughout the entire voltage range, including the low voltage regime. The control system of the prior art is thus unstable and difficult to control accurately due to the uncontrollable region.